Typically, scan-based diagnosis of electronic circuits comprises scan chain diagnosis and system logic diagnosis. Scan chain diagnosis targets one or more defects in one or more scan chains, while system logic diagnosis targets one or more defects in system logic coupled to the one or more scan chains. Typically, systems perform scan chain diagnosis and system logic diagnosis separately. For system logic diagnosis, it is often assumed that the scan chains are working correctly. Similarly, for software-based scan chain defect diagnosis, it is often assumed that the system logic is defect-free. Hardware-based scan chain defect diagnosis methods, by contrast, typically make no assumptions about the system logic, but require extra hardware overhead to implement special scan architectures.
It is not unusual for scan chain defects and system logic defects to co-exist on one die, resulting in so-called “compound defects” or “mixed defects.” The coexistence of scan chain defects and system logic defects can complicate diagnosis, as diagnosing faulty scan chains can require verifying the functioning of the system logic, but testing the system logic can require properly functioning scan chains. To address this issue, improved fault diagnosis methods that are capable of detecting and identifying compound defects are desired.